Automatic gain control system



l April 1,1, 1950 Y A. BuRNoT 2,503,900A

= Au'ro'ATIc-GAIN CONTROL sYs'ml v Filed Jan. '2a. 19,48A

t --J 'Y L4" Inventor-z Q* f Joseph A. Burho'b,

by@ ,om

His Attorney.

Patented Apr. 11|, 1950 l 2,503,900 AUTOMATIC GAIN CONTROL SYSTEM y Joseph A. Burnot, Paris, France, assignor to General Electric Company, a corporation of New York Application January 2s, 194s, serial No. 4,750 In France December 29, 1943 Section 1, Public Law 690, August 8, 1946 Patent expires December 29, 1963 (Cl. Z50-20) 2 Claims.

My invention relates toan automatic gain control system and is particularly applicable to automatic gain control circuits of a radio receiver.

It is a principal object of my invention to provide an improved automatic gain control system which operates effectively over a very wide range of input signal voltages. Briefly, thisis accomplished in accordance with the invention by deriving two independently adjustable, delayed automatic gain control potentials from the detected signals. The first of these potentials is developed when the amplitude of the detected sig,- nals exceeds a rst threshold level and is utilized primarily to regulate the gain of preceding high frequency and intermediate frequency amplifier stages. The second of these potentials is developed only when the signal level exceeds a second, higher threshold value and is utilized to regulate the gain of a succeeding signal frequency amplifier stage.

It is a further object of. my invention to provide an improved automatic gain control system for a radio receiver which combines a plurality of control actions in order to provide most effective operation over a very wide range of sgnal conditions.

Still another object of my invention is to provide an improved automatic `gain control system for an amplitude-modulation signal receiving system which requires a minimum of circuit components and adjustments and yet provides a highly elfective gain limiting action.

For additional objects and advantages, and for a better understanding of the invention, atten tion is now directed to the following description and accompanying drawing, and also to the appended claims in which the features of the invention believed to -be novel are particularly pointed out.

The single ligure of the drawing is a circuit diagram, partly in simplified schematic block form, of a superheterodyne radio receiver .embodying the invention.

In the accompanying drawing, those elements which particularly relate to the automatic gain control circuits are represented in detail, while the remaining elements of the superheterodyne receiver are merely represented in block form since their details are not material to the invention and it is only necessary to indicate their relationship to the automatic gain control circuits. Amplitude-modulated carrier signals received by antenna I may be amplified n a radio frequency amplifier I I. They are then combined in the usual manner with locally-generated oscillations from oscillator I2 in mixer I3. The intermediate frequency carrier signals are then further amplied in intermediate frequency amplifier I 4 and demodulated in detector I5, after which they are amplified in signal amplifier I6. They lmay then be further ampliiied in a power amplifier Il before being supplied to a suitable translating device such as a loud speaker I8.

Those skilled in the art will recognize that the circuit elements just described are those of the conventional superheterodyne radio receiver and may be subject to considerable variations. Each of the amplifying units Il, I4, and I1 may comprise one or morestages. In some cases the radio frequency amplifier II may be omitted. Where it is used in a tunable system, it is unicontrolled fwith oscillator I2 for proper signal tracking, as indicated by dashed connections I9. One or several of the various stages preceding detector I5 may be supplied with automatic gain control potentials to regulate the gain thereof in the conventional manner, as indicated by connections 25, 26, 21, and 28. The manner in which these and other gain control potentials are developed in accordance with my invention will now be considered in greater detail.

Signal detector I5 is represented as a known form of diode detector circuit comprising an input transformer 30 coupled to the output of intermediate frequency amplier I4, a diode D1, and output load resistors R1 and R2 in series. Resistors R1 and R2 are by-passed for intermediate frequencies in the usual manner by capacitors C1 and C2. The cathode of diode D1 is connected. to ground through a resistor R3 which is by-passed for signal frequencies (for example, audio frequencies) by capacitor Ce. Signal frequencies appearingacross R2 are supplied through blocking capacitor Ca to potentiometer R10.

Signal amplifier` I6 is represented as comprising a pentode 3| having la control grid G1 connected to a tap 32 on .potentiometer R10 through blocking capacitor C7. The cathode is connected to ground through the resistor R3 which, with bypass 'capacitorv C6 forms a self-bias cathode network. Anode and screen grid operating potentials are supplied in the conventional manner from any suitable source, represented conventionally by the symbol B+, through resistors 33 and 34, respectively. Control grid G1 is also connected to ground for direct voltages through a resistance network comprising resistors Rs, R7 and Rs in series. Resistors Re and Rv are also connected between B+ and ground through an additional resistor R9, thus forming a voltage di'- vider network, the function of which will be shortly apparent.

In accordance with my invention the intermediate frequency signals at the output of the transformer 30 are also supplied through coupling capacitor C4 to a gain control detection circuit comprising a diode Dz and load resistors R and Rs. It will be observed that this load circuit also includes the cathode bias network Re and Cs. Network R3, Cs provides a threshold operating level, or delay bias for diode D2 due to the now of space current in pentode 3l. It will be observed that flow of space current through resistor R3 tends to render the -cathode of diode lD2 positive-with respect to ground and to maintain it non-conducting. When the input signal voltages are sufficient to render diode D2 conducting, unidirectional gain control potentials are developed across resistors R5 and Rs and impressed on conductor 25 through a lilter network comprising resistor R4 and capacitor C5. The potentials developed across capacitor C5 are negative with respect to ground, as indicated, and are utilized to reduce the gain of one or more 0i the preceding amplifier stages, as

previously indicated. The time constant oi iilter f network R4, Cs is made relatively long, as is customary, in order to eliminate any low-frequency ripple.

Although the diodes Dr and D2 and the pentode l3i have been represented as separate tubes in order to clarify the disclosure, it will be apparent that they may all be conveniently combined in a single tube of the duplex-diode-pentode type since Aall their eathodes are connectd together.

A third diode D3 is connected between .the junction oi resistors R7, Rs, R9 and ground. This :diode is shunted by a capacitor Cs and is arranged so. as to be normallyconducting in response to the positive potentials supplied from B-lthrough resistor R9. Thus diode D3 provides a low impedance path to complete a connection from grid G1 to ground through resistor Re, so long as it is conducting.

A fraction of the gain control voltage, appearing across resistor Re when diode D2 is conducting, is impressed through the filter R7, Cs on diode Ds. It will be observed that the polarity is such as to oppose the positive bias voltage which normally maintains diode Da conductive.

The system operates as follows: When the amplitude of the signal voltage supplied to transformer 30 increases, starting from zero, no gain control` action takes place so long as the signal level has not reached a deiinite threshold value determined by the voltage :drop across resistor R3. When the voltage exceeds this level and causes diode D2 to conduct, automatic gain control potentials are impressed upon conductor in the manner previously described. The circuit constants are arranged so that the voltage impressed upon diode Ds through resistor R7 is insufficient to overcome its positive bias until a second higher signal level is reached. Thus the diode D3 remains conducting and the signal amplifier 6 continues to operate without substantial reduction in amplincation until this second, higher threshold level is reached. Finally, when the detected signal voltage impressed upon diode Da becomes suf.- cient, the latter is rendered non-conducting and the regulating voltage is applied to the control grid of tube 3l as well as to the preceding receiver stages, reducing its gain as well.

By a suitable selection of the ratio between resistors R5 and Re, it is possible to obtain almost perfect regulationin this third operating range.

In an apparatus built in accordance with the above description, a rst operating threshold was obtained for an input voltage of about 50 microvolts, and the second threshold at about 1000 microvolts. There was no regulating eiect in the first part of the regulation curve, that is to say, between about 10 and 50 microvolts. The regulating eiect between about 50 and 1000 microvolts was such that the input level had to be varied by 4 decibels in order to obtain a variation in the .output level amounting to 1 zdecibel. Finally, in the last operating zone, which lay between about 1000 microvolts and 1 volt, the slope of the gain control curve was such that it would have been necessary to vary the input level by about 80 decibels in order to obtain a variation in the output level amounting to 1 decibel. These iigures are purely illustrative, but they serve to bring out the extremely ydesirable operating characteristics of the system embodying my invention.

It is, oi course, evident that the automatic gain `contr-ol circuits of my invention are applicable to other types of receiving apparatus as well as to a superheterodyne receiver, regardless of whether they are used for radio communication or other high frequency transmission.

While a speciiic embodiment has been shown and described, it will of course be understood that various modifications may be made without departing from the invention. The appended claims are therefore intended to cover any such modications within the true spirit and scope of the invention.

What I claim as new and desire to secure by Letters Patent of the United States is:

1. The combination, in a receiving system of the type including a carrier Wave amplifier, a detector for demodulating the amplied carrier waves and a signal amplifier to which the detected signals are supplied, said signal amplier having a self-bias cathode impedance, of a control circuit including a rectier and load impedance for developing gain control potentials on said load impedance in response to said carrier Waves, means for impressing a delay bias on said circuit derived from said cathode impedance, whereby said potentials are developed only when said carrier waves exceed a rst level dependent upon said self-bias, means for applying said potentials to said carrier wave amplier in a sense to reduce the gain thereof, means for additionally impressing said potentials on said signal wave amplier in a sense to reduce the gain thereof, and means comprising a second rectifier normally biased to conducting condition for preventing application of said potentials to said signal amplifier until they exceed a value corresponding to a second higher carrier level at which said second rectier is cut off.

2. The combination, in a receiving system of the type including a carrier wave amplier, a detector for demodulating the amplied carrier waves and a signal ampliiier to which the detected signals are supplied, said signal amplifier having a self-bias cathode impedance, of a control circuit including a rectifier and load impedance for developing gain control potentials on said load impedance response to said carrier waves, means for impressing a delay bias on said circuit derived from said cathode impedance, whereby said potentials are developed only when said carrier waves exceed a i'lrst level dependent upon said self bias, means for applying said potentials to said carrier wave amplifier in a sense to reduce the gain thereof, means for additionally impresaooaob'oo sing gain control potentials developed across only a portion of said load impedance upon said signal ampler in a sense tending to reduce the gain thereof, a second control circuit including a second rectifier connected in shunt relation to said portion, said second rectiier being poled to be rendered nonconductive by the potentials developed across said portion; and means for applying a. predetermined positive ybias potential to said second rectier adjusted to maintain it conductive until said potentials across said portion exceed a value corresponding to a second, higher signal level, thereby t prevent application of said potentials to said signal amplier until they exceed said second level. il

JOSEPH A. BURNOT.

REFERENCES CITED following references are of record in the vvfiieof this patent:

' UNITED STATES PATENTS Name Date Wheeler Sept. 3, 1935 Franks Apr. 13, 1937 Holst May 17, 1938 Koch Jan. 17. 1939 Koltz May 23, 1939 Koltz Sept. 5, 1939 Getaz -s July 9, 1940 

